1. Field of the Invention
This invention relates to improved integrated circuit devices a more particularly, to an improved integrated circuit device for use in a thermal ink jet printhead which contains active logic and driver devices, along with passive resistive heater elements and a method for making the integrated circuit device.
2. Description of the Prior Art
Drop-on-demand thermal ink jet printers are generally well known, and in such systems, a thermal ink jet printhead comprises one or more ink filled chambers communicating with an ink supply chamber and an array of orifices, generally referred to as nozzles. A plurality of thermal transducers, usually resistors, are located in the channels at a predetermined location relative to the nozzles. The resistors are individually addressed with a current pulse to momentarily vaporize the ink in contact therewith and form a bubble which expels an ink droplet. As the bubble grows, the ink bulges from the nozzle and is contained by the surface of the ink as a meniscus. As the bubble begins to collapse, the ink between the nozzle and the bubble starts to move towards the collapsing bubble, causing a volumetric contraction of the ink at the nozzle and resulting in the separation of the bulging ink as a droplet. The acceleration of the ink out of the nozzle while the bubble is growing provides the momentum and velocity required for the droplet to proceed in a substantially straight line direction towards a recording medium, such as paper.
A typical thermal ink jet printhead for use in an ink jet printer comprises an ink flow directing component, such as an etched silicon substrate which contains a linear array of channels open at one end and a common reservoir in communication with the channels, and a logic and thermal transducer component, such as a substrate which contains a linear array of heating elements, usually resistors, and monolithically integrated logic drivers. The components are aligned and mated with one resistor in each channel a predetermined distance from the channel open end; the channel open ends serving as the droplet expelling nozzles. Power MOS drivers immediately next to and integrated on the same substrate as the array of resistors are driven by logic elements, also integrated on the same substrate, that selectively enable the drivers which apply electrical pulses to the resistors. One known method of fabricating thermal ink jet printheads is to form a plurality of the ink flow directing components and a plurality of logic, driver, and thermal transducer components on respective silicon wafers, and then aligning and bonding the wafers together, followed by a process for separating the wafers into a plurality of individual printheads, such as by dicing. The number of sets of logic, driver, and thermal transducer components which may be formed on a wafer establishes the number of printheads that can be obtained from a wafer pair. Therefore, reduction in any portion of the logic, driver, and thermal transducer component will shrink the size of the printhead, increasing the number per wafer and, consequently, increasing the printhead yield per wafer pair, with the result of lowering manufacturing costs.
Combining driver and transducer elements on a single chip using standard NMOS process steps is exemplified by U.S. Pat. No. 4,947,192 to Hawkins et al., which discloses a monolithic silicon integrated circuit for a thermal ink jet printer wherein a MOS transistor and resistor are formed on the same substrate. The reference indicates the potential for adding logic circuitry capable of addressing an arbitrarily large number of ink jets with minimal electrical connections. Such a monolithic device, having logic elements, drivers, and transducers incorporated therein, would generally require added photoresist masking and implant steps to produce enhancement and depletion mode logic devices. A device of this type is achieved using a single polysilicon layer. Specifically, the source-drain n-type contacts are doped with arsenic, while polysilicon is doped with phosphorous to create a low resistivity (25 .OMEGA./.quadrature.) material at the ends of the transducers. The method constitutes an eleven mask step process to create the structure.
Power MOS devices are suited for the thermal ink jet power applications, because of superior switching speeds and higher voltage breakdown characteristics. However, a power MOS device is limited by its sensitivity to mobile ions such as Na.sup.+, Li.sup.+, and K.sup.+, commonly found in inks used by thermal ink jet printers. The sensitivity of MOS devices to ions is due to the mobility of these ions in SiO.sub.2 as charged species that drift in the presence of an applied electric field, such as those created by a biased gate or metallization layer. These drifting ions in MOS devices cause unstable logic operation as evidenced in shifting threshold voltages and premature breakdown of high voltage devices. Since the inks used for thermal ink jet printing have mobile ions as part of their dye species and because mobile ion drift is accelerated by the high operational temperatures of the printhead, electronic circuitry resident in the printhead must be protected from the ink.
U.S. Pat. No. 5,010,355 to Hawkins et al. discloses an improved ink jet printhead having ionic passivation of integrated MOS circuitry which is exposed to ink. The improvement is obtained through the deposition of a multi-layered, thin film insulated coating consisting of a first layer of doped or undoped silicon dioxide having a thickness of 200 angstroms to 2 microns followed by a second layer of plasma nitride having a thickness of 1000 angstroms to 3 microns. The silicon nitride is etched from the protective layers, usually Ta, over the resistor elements and electrical contact pads for external connection to electrical power, so that the first layer of silicon oxide is exposed, followed by etching of the silicon oxide to remove it also from the protective layers and contact pads. Thus, the MOS circuitry is protected from mobile ions in the ink by the multi-layered coating, while substantially the same fabrication process of a printhead is maintained. In an alternative embodiment, the multi-layered ionic passivation comprises three thin film layers with a final polyimide layer interfacing with ink.
Further improvements to device fabrication techniques are exemplified by U.S. Pat. No. 5,075,250 to Hawkins et al. which discloses an improved NMOS fabrication technique that is more cost effective and provides more reliable and compact elements. The fabrication technique has high yields and enables monolithic integration of logic drivers and transducer elements. The improvement is related to methods by which mask and implant steps can be combined to reduce the number of critical processing steps. Specifically, it is directed at replacing separate arsenic source-drain and phosphorous polysilicon masking and implant steps with a single phosphorous masked implant step. It further eliminates a second mask level by self-aligning the boron substrate contact to the etched vias in the reflow glass layer.
Improved thermal ink jet fabrication techniques with a reduced process sequence have enabled a high yield production of monolithic integrated logic, driver and transducer elements. However there continues to exist a need for an improved fabrication sequence that allows substantial shrinkage of the thermal ink jet die. For example, by increasing the transconductance of devices without decreasing the breakdown voltage, the size of the drivers may be reduced so that the number of die per wafer increases, which correspondingly decreases printhead cost. Since power MOS drivers account for approximately 40% of thermal ink jet die area, significant die savings can be achieved by increasing the efficiency of the driver element. Tradeoffs, however, are made when fabricating power (high voltage) MOS devices with comparable or increased transconductance and decreased size. Generally, as the transconductance of a power MOS device is increased with heavier drift region doping, the breakdown voltage decreases. Two arrangements of lateral power MOS drivers are offset gate and field plated power MOS drivers, both of which are exemplified in the above-mentioned U.S. Pat. No. 4,947,192 to Hawkins et al. Emphasis has been placed on producing offset gate power MOS drivers since they require fewer process steps to fabricate and typically consume less space, making them more readily implemented under the design constraints faced by thermal ink jet printheads.
Although current field plated power MOS drivers consume greater chip surface area than comparable offset gate power MOS drivers, field plated power MOS drivers have attractive performance attributes which can lead to further shrinkage of thermal ink jet dies. In operation, when a potential is applied across the drain and source of a field plated driver, the drift layer is pinched or depleted of carriers between the grounded wafer and the grounded field plate. Field strength at the drift region to channel region is greatly reduced by the field plate placed over the drift region, which thereby controls the breakdown voltage of the device while increasing its transconductance. For example, Buhler et al., "Integrated High-Voltage/Low-Voltage MOS Devices", IEDM, 1981, p. 259, discloses a high voltage device structure and a corresponding fabrication process that utilizes a highly resistive field plate to control device breakdown and transconductance. The polysilicon is differentially doped to be conductive in the contact areas to the drain and gate and is highly resistive over the drift area. Martin et al., "805V NMOS Driver with Active Outputs", IEDM, 1984, p. 266, further disclose an improved high voltage device by adding an additional layer of polysilicon and lightly doping the silicon underneath the field plate (drift layer). One layer of the field plate has a high sheet resistance to set the surface potential of the drift region. In both devices, the field plate is over a thick field oxide layer. Although the improvements brought forth by Buhler and Martin provide high voltage field plated power MOS devices, they do not meet thermal ink jet MOS driver size or current handling requirements. In addition, their fabrication process to define the drift layer does not enable rework of the photolithography. Thus, although improvements have been made, there continues to exist a need to reduce the size of high voltage field plated devices, while providing a transconductance comparable to current offset gate devices with no attendant loss in breakdown voltage.